PROCEDURE - DETERMINATION OF THE WAVELENGTH OF RED AND GREEN LASERS USING LAB GRATING

Comparison Between Huygens and Ramsden Eyepieces

 

First 100 Binary Numbers with Decimal Equivalents

First 100 Binary Numbers with Decimal Equivalents

Decimal	Binary	Decimal	Binary	Decimal	Binary	Decimal	Binary	Decimal	Binary
0	00000000	1	00000001	2	00000010	3	00000011	4	00000100
5	00000101	6	00000110	7	00000111	8	00001000	9	00001001
10	00001010	11	00001011	12	00001100	13	00001101	14	00001110
15	00001111	16	00010000	17	00010001	18	00010010	19	00010011
20	00010100	21	00010101	22	00010110	23	00010111	24	00011000
25	00011001	26	00011010	27	00011011	28	00011100	29	00011101
30	00011110	31	00011111	32	00100000	33	00100001	34	00100010
35	00100011	36	00100100	37	00100101	38	00100110	39	00100111
40	00101000	41	00101001	42	00101010	43	00101011	44	00101100
45	00101101	46	00101110	47	00101111	48	00110000	49	00110001
50	00110010	51	00110011	52	00110100	53	00110101	54	00110110
55	00110111	56	00111000	57	00111001	58	00111010	59	00111011
60	00111100	61	00111101	62	00111110	63	00111111	64	01000000
65	01000001	66	01000010	67	01000011	68	01000100	69	01000101
70	01000110	71	01000111	72	01001000	73	01001001	74	01001010
75	01001011	76	01001100	77	01001101	78	01001110	79	01001111
80	01010000	81	01010001	82	01010010	83	01010011	84	01010100
85	01010101	86	01010110	87	01010111	88	01011000	89	01011001
90	01011010	91	01011011	92	01011100	93	01011101	94	01011110
95	01011111	96	01100000	97	01100001	98	01100010	99	01100011

Message Encryptor and Decryptor

About This Encryptor

This is a simple encryptor designed for demonstration purposes only. It uses the following character set as the symbol set for a base-92 number system:

{ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789 .,!;:'{}()[]="\%&#*+-/@$?_|\n\t}
          

How It Works:

1. Encryption:
   • The message and pass-key are converted from base-92 into decimal integers.
   • The decimal integer representing the message is multiplied by (pass-key decimal integer + 1).
   • The resulting decimal integer is posted as the encrypted message in the text box.
2. Decryption:
   • The decryption process reverses the above steps.
   • If the pass-key is incorrect, the decrypted message will appear as a meaningless string of characters from the base-92 set.

Important Notes:

• This encryptor is intended for learning and experimentation only.
• Do not use it for sensitive or professional data.
• The author is not responsible for any misuse of this application.

Please ensure your data is secure and exercise caution when using this tool.

Message Encryptor and Decryptor

⧪ Message ⧪

Pass Key

Postulates of Geometrical Optics

1. Light travels in straight lines in a homogeneous and isotropic medium.

2.When light reflects off a smooth surface, the angle of incidence is equal to the angle of reflection. The incident ray, reflected ray, and the normal to the surface at the point of incidence lie in the same plane.

3.When light passes from one medium to another, it bends according to Snell's Law:

where n₁ and n₂ are the refractive indices of the two media, and θ₁ and θ₂ are the angles of incidence and refraction, respectively.

4. The path of a light ray is reversible. If a ray of light follows a path from point A to point $B$, it will follow the same path in reverse when traveling from $B$to $A$.

5.Light rays do not interact with each other when they cross. The intensity at a point is the algebraic sum of the intensities of individual rays.

6.Light travels between two points along the path that requires the least time, which may be a straight or curved path depending on the medium.

Decimal to Roman Numerals Converter

Decimal to Roman Numerals Converter

Enter a Decimal Number

Fermat's Principle of Least Time

Fermat's Principle of  Least Time : The path taken by light between two points is the path that requires the least time, compared to nearby paths.

Hero's Principle of Shortest Distance

Hero's Principle of  Shortest Distance : The path taken by light between two points is the path that requires the shortest distance, compared to nearby paths.

Consolidated Question Bank - Integrated Electronics - 23BPH6E1

UNIT - I
PART A - 2 MARK QUESTIONS

1.Convert the following :

(a) The hexadecimal (306.D)₁₆ into binary.

(b) The binary (110.111)₂ into decimal.

2.What is the truth table for the EX-OR gate?
3.Convert (625)₁₀ into binary numbers?

4.Draw Logic circuits for Y = ABC + ABC.

6.Convert (10101101)₂ do decimal number system.

7.Give the logic symbol and truth table of EX-OR gate./Write the truth table for a 2-input XOR - gate./Write the truth table for a 2-input XOR - gate.

8.Convert (45.5)₁₀ to binary number.
9.Simplify Y = ABC + ABC + ABC + ABC

10.Convert (498)₁₀ to hexadecimal number.

11.Simplify Z=(A+B).(A+B)

12.Convert (a) (24.125)₁₀ = (?)₂ (b)(1001100111)₂ = (?)₁₆

13.Define binary logic gate.

14.State De Morgan’s theorem.

15.(109)₁₀ = (X)₈. Find X.

16.Draw the symbol of NOT and EX-OR gate.

17.What are the four main number systems used in digital electronics?.

18.Convert the decimal number 25 into binary, octal, and hexadecimal systems.

19.Perform binary addition for (1011)₂+(1101)₂

20.Explain the 1’s complement method for binary subtraction.

21.What is the 2’s complement of the binary number (101011)₂?

22.What is a BCD (Binary Coded Decimal)? Give an example.

23.Simplify the Boolean expression A+AB using Boolean algebra.

24.Convert the hexadecimal number 1F into binary.

25.Describe the steps involved in binary multiplication, (1101)₂ x (101)₂

PART B - 5 MARK QUESTION

1.Verify that the following operations arecommutative and associative.

(i) AND (ii) OR.

2.Explain how BCD addition is carried out? What decimal number does the BCD sequence 0110 11101100 0010 1101 represent?

3.Using Boolean algebra techniques, simplify the

following expressions as mush as possible.

(i) A(A + B)

(ii) A(A+ AB)

4.Applying De-Morgan’s theorem, simplify the following:

Y = (A+B) + C

Y = (A+B) C D + E + F

5.Convert the decimal number 724 to hexadecimal and binary number system.

6.State and prove De-Morgan’s theorem./State and prove De-Morgan's theorems/.State and prove De-Morgan’s theorem with truth table./State and prove De Morgan’s theorem.

7.Convert

(i) (498)₁₀ =(?)₁₆

(ii) (A7.3B)₁₆=(?)₈

8.Convert : (1110.0110)₂ to decimal and (2497.50)₁₀ to octal

9. Convert the given hexadecimal number into octal and binary numbers (2ED)₁₆ = (?)₈ = (?)₂

10.Explain basic gates with their truth tables./Explain the function of basic logic gates.

11.What is a BCD (Binary Coded Decimal)? Explain its importance and convert the decimal number 93 to its BCD equivalent.

12.Convert the given octal number into decimal and hexadecimal number, (516)₈ = (?)₁₀ = (?)₁₆

PART C - 10 MARK QUESTIONS

1.Explain EX-OR gate and give its truth table. Draw the logic diagram of EX-OR gate? Describe the operation of the gate.

2.(a) Draw the logic symbol of NAND and NOR gates. Give its truth table.

(b) What do you mean by associative law and distributive law?

3.State and prove De-Morgan’s theorem./State and prove De-Morgan's theorems/.State and prove De-Morgan’s theorem with truth table./State and prove De Morgan’s theorem.

UNIT - II

PART A - 2 MARK QUESTIONS

1.Using NAND gates, construct the following Logic circuits

Y = AB +BC

Y = AB + CD

2.How Karnaugh map is useful?
3.Define : Octet.

4.What is meant by SOP and POS?
5.What is meant by don’t care condition?

6.Why are NAND and NOR gates called universal gates?

7.What is a Karnaugh map (K-map)?

8.Simplify the Boolean expression AB+AB+AB using a Karnaugh map.

PART B - 5 MARK QUESTIONS

1.Write a short note on 2, 3, 4 variables Karnaugh map.
2.Why NAND gate is called Universal building block? Explain with example.
3.Minimize the following Boolean functions and use AND, OR, NOT circuits

f(A ,B ,C ,D) = Sigma(0, 2,7,8,9,3)+Don'tCare(0,10,12,14)

4.Simplify the following expression using K-map.

f(A,B,C,D) = Sigma(0,1,4,5,6,8,9,10,11,12,13,14)

5.Reduce using K - map:

Y=f(A,B,C,D)=Sigma(2,5,7)+Don't Care(3,6)

6.Draw the circuit for the following Boolean expression F = (A + B )(CD+ E) using only NAND gates.

7.Define the Sum of Products (SOP) method with an example.

8.Draw the circuit for the following Boolean expression F = A (B + CD) + BC with only NOR gates.

9.Draw and explain the truth tables for the three basic logic gates: AND, OR, and NOT.

10.Explain the XOR gate with its logic symbol, truth table, and Boolean expression.

11.Simplify the given Boolean expression using a Karnaugh map: F(A,B,C)=AB+AC+BC

$\mathrm{<span\; style="text-align:\; justify;">12.Explain\; the\; “don’t\; care\; condition”\; in\; a\; K-map\; with\; an\; example\; of\; how\; it\; simplifies\; a\; Boolean\; function.</span>}$

PART C - 10 MARK QUESTIONS

1.Draw and explain NOR and NAND gate with its truth table. Why is NAND gate called a universal building block? Explain./ Explain how basic gates are obtained from NAND and

NOR gates./Prove that NAND and NOR as universal gate./Prove that NAND and NOR gates as Universal gates./Explain the function of NAND gate as universal gates.

2.Simplify the Boolean function F(W, X, Y, Z) = Σ(1,3,7,11,15) that has the don’t care condition d(W,X,Y,Z)=Σ(0,2,5)

3.Using K-map simplify and draw AND–OR network for the reduce expression

Y = F(A,B,C,D) =Σ(0,1,2,4,5,10,11,12,14,15) + d(3,6,13)

4.Simplify using K-Map and draw NAND-NAND network for the reduced expression :

Y = F(A,B,C,D) =Σ(1, 11, 13, 14, 15) + d(3, 5, 7, 9, 10)

5. Using K-Map Y = F(A,B,C) = Σ0, 1, 4, 5) and Draw AND-OR Gate form.

6.Simplify the Boolean expression Σ (1,2,3,8,9,10,11,14) + d (7,15) using K-map.

UNIT - III
PART A - 2 MARK QUESTIONS

1.Distinguish between half adder and full adder.

2.What do you mean by a full adder?/What is a Full Adder?

3.Give the expression for sum and carry for Half–adder with circuit.

4.Define : Half subtractor.
5.Draw Half-adder circuit.

6.What is a multiplexer, and why is it used?

7.Define a demultiplexer and mention its application.

8.What is the function of a 1 of 16 decoder?
9.Explain the purpose of a BCD to decimal decoder.

10.What is a seven-segment decoder, and where is it commonly used?

11.What is an encoder, and how does it differ from a decoder?

12.What is the logic function of an Exclusive OR (XOR) gate?

13.What is a parity generator?/What is the purpose of a parity checker in digital circuits?

14.Define a 4-bit adder/subtractor. How is subtraction performed in such a circuit?

15.State the difference between a multiplexer and a demultiplexer.

16.How does a half subtractor differ from a full subtractor?
17.Explain the role of a BCD to decimal decoder in digital systems.

18.What is the primary advantage of using a 4-bit adder/subtractor circuit?

PART B - 5 MARK QUESTIONS

1.Explain half adder and full adder.
2.With a neat logic diagram explain about full subtractor./Draw Full subtractor circuit and write its truth table.
3.Explain full adder circuit and write its truth table.

4.Explain the function of half adder and half subtractor with suitable circuit.

5.Explain the working principle of a multiplexer with a neat diagram.

6.Describe the operation of a demultiplexer.

7.Explain the design and working of a 1 of 16 decoder with a truth table.

8.Describe the functionality of a BCD to decimal decoder with an example.

9.Explain how a seven-segment decoder works and its application in digital displays.

10.Differentiate between an encoder and a decoder with examples.

11.Explain the working of a parity generator and parity checker with suitable logic diagrams.

12.Describe the design and operation of a 4-bit adder/subtractor circuit. Explain how subtraction is performed using it.

PART C - 10 MARK QUESTIONS

1.Draw the following circuits and explain its operation :

(a) Parallel binary adder.

(b) Parallel subtractor.

2.How a half adder and a half subtractor circuits are working? Explain with its truth table.

3.Explain the working of half and full adder with neat circuit diagram.

4.Explain in detail the working of a multiplexer. Design a 4-to-1 multiplexer circuit with a truth table and logic diagram.

5.Describe the construction and working of a demultiplexer. Compare its operation with a multiplexer and discuss their applications.

6.Design and explain the working of a 1 of 16 decoder. Include the truth table and practical applications in your explanation.

7.Design and explain the working of a 1 of 16 decoder with the truth table and applications.

8.Explain the working of a parity generator and parity checker. Discuss their importance in error detection in digital communication.

9.Describe the circuit design and functionality of a 4-bit adder/subtractor. Explain how binary addition and subtraction are performed using this circuit.

10.Discuss the working and differences between half adder, full adder, half subtractor, and full subtractor with appropriate logic diagrams and truth tables.

UNIT - IV
PART A - 2 MARK QUESTIONS

1.What is a synchronous counter?

2.State any two differences between RS Flip flop and JK Flip flop.
3.What is shift register?/What do you mean by shift register?

4.Give the symbol of RS flip flop with its truth

table.
5.What is a D–flip flop?

6.Define : Flip-Flop./What is a Flip flop?

7.List the different types of Shift Registers.

8.Define registers.
9.Define counters.
10.List the different types of Flip- Flops.

11.What is an R-S flip-flop, and w

hat are its basic functions?

12.What is the key difference between a JK flip-flop and an RS flip-flop?

13.What is a JK master-slave flip-flop, and why is it used?

14.Define synchronous and ripple counters. How do they differ?

15.What is a BCD counter?

16.Explain the purpose of an up/down counter in digital systems.

17.What are shift registers, and what is the difference between serial and parallel registers?

18.What is a ring counter, and how does it differ from a twisted ring counter?

PART B - 5 MARK QUESTION

1.Explain the action of a shift register. How they are classified?
2.Explain the working principle of Master – Slave JK – FF.
3.Draw the clocked RS flip flop and explain with truth table.

4.What are the difference between R-S flip flop using

(i) NAND and (ii) NOR gates.

5.How will you drive D flip flop from a RS flip flop? Give example.

6.Construct a shift left shift register and explain its working./Explain about shift resister.

7.With a neat block diagram, explain about a ripple counter./Describe the working of a 4-bit Ripple counter./ Describe ripple counter

8.Explain the working of clocked RS –flip flop./Explain the function of RS flip flop./Explain the working of an RS flip-flop with a truth table and logic diagram.

9.Describe the working of 3-bit shift register.

10.Explain the action of clocked D flip-flop.

11.Describe the action of Ring Counter./What is a Ring counter? Explain its working.

12.List the different types of counters.

13.What are shift registers? Explain the working of serial-in serial-out and parallel-in parallel-out registers.

14.Describe the operation of a D flip-flop/

15.Explain the construction and working of a JK flip-flop with a neat diagram and truth table.

16.Describe the operation of a JK master-slave flip-flop and its advantage over a simple JK flip-flop.

17.Differentiate between synchronous counters and ripple counters.

18.Explain the design and working of a BCD counter.

19.Describe the construction and application of an up/down counter.

20.Explain the operation of a ring counter and a twisted ring counter with block diagrams.

PART C - 10 MARK QUESTIONS

1.Explain the logic diagram of SR Flip-Flop.

2.Explain the function of JK Flip-Flop in detail./Explain the logic diagram of J-K Flip-Flop./Explain the working of a JK flip-flop with its truth table, timing diagram.

3.Discuss the design and working principle of a JK master-slave flip-flop. Highlight its advantage over a simple JK flip-flop and provide examples.

4.Design and draw the 3 bit up-down synchronous counter.

5.Explain the construction and working of an RS flip-flop and its applications. Discuss the invalid state in detail with examples.

6.Describe the design and operation of a D flip-flop.

7.Differentiate between synchronous and ripple counters. Design a 4-bit synchronous counter and explain its operation step by step.

8.Describe the working of a shift register. Explain the operation of serial-in serial-out (SISO) and parallel-in parallel-out (PIPO) shift registers with block diagrams.

9.Explain the design and operation of a ring counter and a twisted ring counter. Discuss their differences and applications in digital systems.

UNIT - V
PART A - 2 MARK QUESTIONS

1.Why A/D and D/A converter are needed?

2.Define conversion time of an A/D converter.
3.Write a short note on D/A accuracy and resolution.

4.What is accuracy?/Define the term accuracy.
5.What is differential linearity in ADC?/Define Differential linearity.

6.Define : DAC Resolution./Define the term resolution.

7.What is meant by ‘Quantization Error’ in ADC?

8.What is meant by Propagation delay?
9.Mention the types of DAC.
10.List the drawbacks of binary weighted resistor method of

D/A conversion.

11.What is the function of a 555 timer IC in electronic circuits?

12.What are the three modes of operation of the 555 timer?

13.What is the function of the control voltage pin in a 555 timer?

14.Define a monostable multivibrator and its primary application.

15.What is the purpose of a bistable multivibrator in digital electronics?

16.Define an astable multivibrator and mention one application.

17.What is the purpose of a Schmitt trigger circuit?

18.What is a binary ladder D/A converter?

19.What is an A/D converter?

20.What is the difference between simultaneous conversion and successive approximation methods in A/D conversion?

21.What is the role of a variable resistor network in D/A converters?

22.Explain the term "successive approximation" in A/D conversion.

23.What is the main advantage of using a Schmitt trigger in a circuit?

PART B - 5 MARK QUESTIONS

1.Explain the working of binary – weighted resistor type D/A converter./Draw the diagram of binary – ladder network? Explain how this can be used as a DAC./Describe the working of a binary ladder DA converter./Obtain an expression to find the output voltage from the binary ladder./Explain the resistance characteristics of a 4-bit binary ladder.

2.Explain the working and principle simultaneous A/D converter?/Explain simultaneous method of ADC.

3.Write a short on successive approximation method./Explain the working of successive approximationAD converter/Explain the working of successive approximation

type A/D convertor.

4.Define the following performance parameters of D/A

converters:

(i) Resolution

(ii) Conversion Time and

(iii) Monotonicity

5.Explain the internal block diagram of the 555 timer and describe its key components.

6.Describe the working of an astable multivibrator using the 555 timer with a neat circuit diagram.

7.Explain the operation of a monostable multivibrator with a 555 timer and mention its applications.

8.Describe the successive approximation method of A/D conversion and its advantages.

9.Explain the Schmitt trigger circuit and its significance in waveform shaping.

PART C - 10 MARK QUESTIONS

1.Describe the successive approximation type A/D converter./Describe the working of successive approximation ADC./Explain the working of successive approximation ADC.

2.Explain the action of asynchronous 4-bit Ripple counter.

3.Explain the action of simultaneous conversion ADC.

4.Explain the internal block diagram of the 555 timer in detail and discuss its working in astable, monostable, and bistable multivibrator modes with circuit diagrams.

5.Describe the working of a binary ladder D/A converter with a neat circuit diagram. Explain the significance of accuracy and resolution in D/A conversion.

6.Discuss the principle and operation of the successive approximation method in A/D conversion. Highlight its advantages over other methods.
7.Explain the design and operation of a Schmitt trigger circuit using a 555 timer. Discuss its applications in signal conditioning.
8.Compare simultaneous A/D conversion and successive approximation A/D conversion methods. Discuss their working principles, advantages, and limitations.

Lecture and Laboratory Schedule for KAZ - 2024-2025 Even Semester

Day Order/ Hour	I	II	III	IV	V
I	III P – KAZ [IE]	II P – KAZ [OPTICS]
II		III P – KAZ [IE]			III P – KAZ [IE]
III	II P PRACTICAL [PKA + KAZ]				III P – KAZ [IE]
IV		III P – KAZ [IE]		II P – KAZ [OPTICS]
V		III P – PROJECT [PKA + KAZ]			III P – KAZ [IE]
VI		III P – PROJECT [KAZ + SJ]			II P – KAZ [OPTICS]