Notes for IV and V Unit - Left out in the Material

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CD – LASER RW Systems

CD stands for Compact Disk and denotes an optical storage medium used to store video, audio and data. CD-ROM disks can be written once and only read thereafter. CD ROM drive uses LASER technology to read data from it.  A semiconductor LASER generates a high intensity light wave of stable wavelength = 780 nm. A lens system is used to direct the LASER towards the disk over approximately 1 micron diameter spot as shown in the figure.

The intensity of the reflected light from metallic reflection layer, received by photo sensors gives the information of binary data stored in CD. There are two different surfaces called land and bit from which reflection occurs. The pit is approximately 0.12 micron deep compared to land and reflected intensities are about 25 % and more than 70 % respectively (Figure b).  

Every time laser beam travels from land to pit or pit to land there is a change in intensity of reflected light.  This change is read as binary digit 1 and a constant intensity reflected light is interpreted as 0. The pit width is such that there is at least 2 and at most 10 zeroes between every 1.  This is achieved by converting every 8-bit byte into a 14-bit value, a process called Eight to Fourteen Modulation (EFM).  Such arrangements make it easy for the read laser to detect bits and synchronization. Data corresponding to a small portion of the track is shown above label in Figure a.

CD-RW

CD-RW or CD-Read Write gives user facility to write and erase data many times. CD-RW uses an active layer of Ag-In-Sb-Te alloy that has a poly crystalline structure making it reflective (reflectivity 25 %). Writing data on disk uses highest power of laser that heats up selected spots to 500°C – 700°C.  At this temperature the chemical structure liquefies losing its polycrystalline structure and on cooling solidifies to an amorphous state that has reduced reflectivity of 15 %. The reading process is like CD-ROM and CD-R that notes the differences in reflectivity of the storage surface.

To reverse the phase or erase data, the laser operates at a lower power setting and heats the active material to nearly 200°C. This reverses the material from its amorphous to its polycrystalline state and then becomes reflective again.  This is illustrated in the following figure.

Flash Memory Notes

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Flash Memory (Memory Stick)

Flash memory storage is a form of non-volatile memory that was born out of a combination of the traditional EPROM and E²PROM.

In essence it uses the same method of programming as the standard EPROM and the erasure method of the E²PROM.

One of the main advantages that flash memory has when compared to EPROM is its ability to be erased electrically. However it is not possible to erase each cell in a flash memory individually unless a large amount of additional circuitry is added into the chip. This would add significantly to the cost and accordingly most manufacturers dropped this approach in favor of a system whereby the whole chip, or a large part of it is block or flash erased.

Today most flash memory chips have selective erasure, allowing parts or sectors of the flash memory to be erased. However any erasure still means that a significant section of the chip has to be erased.

Flash memory is able to provide high density memory because it requires only a few components to make up each memory cell. In Each Flash memory cell consists of the basic channel with the source and drain electrodes separated by the channel about 1 µm long. Above the channel in the Flash memory cell there is a floating gate which is separated from the channel by an exceedingly thin oxide layer which is typically only 100 Å thick. It is the quality of this layer which is crucial to the reliable operation of the memory.

Above the floating gate there is the control gate. This is used to charge up the gate capacitance during the write cycle.

The Flash memory cell functions by storing charge on the floating gate. The presence of charge will then determine whether the channel will conduct or not. During the read cycle a "1" at the output corresponds to the channel being in its low resistance or ON state.

Programming Flash memory

Programming the Flash memory cell involves a process known as hot-electron injection. When programming the control gate is connected to a "programming voltage". The drain will then see a voltage of around half this value while the source is at ground. The voltage on the control gate is coupled to the floating gate through the dielectric, raising the floating gate to the programming voltage and inverting the channel underneath. This results in the channel electrons having a higher drift velocity and increased kinetic energy.

Collisions between the energetic electrons and the crystal lattice dissipate heat which raises the temperature of the silicon. At the programming voltage it is found that the electrons cannot transfer their kinetic energy to the surrounding atoms fast enough and they become "hotter" and scatter further afield, many towards the oxide layer. These electrons overcome the 3.1 eV (electron volts) needed to overcome the barrier and they accumulate on the floating gate. As there is no way of escape they remain there until they are removed by an erase cycle.

The erase cycle for Flash memory uses a process called Fowler-Nordheim tunneling. The process is initiated by routing the programming voltage to the source, grounding the control gate and leaving the drain floating. In this condition electrons are attracted towards the source and they tunnel off the floating gate, passing through the thin oxide layer. This leaves the floating gate devoid of charge.

Generally the erase process is only made to last a few milliseconds. When complete each Flash memory cell in the block is checked to ensure it has been completely erased. If not a second erase cycle is initiated.

Flash memory access

Flash memory is different to most other types of electronic memory in that while reading data can be performed on individual addresses on certain types of flash memory, erase and write activities may only be performed on a block of a Flash memory. A typical block size will be 64, 128, or 256 kB. In order to accommodate this, the low level control software used to drive Flash memories, needs to take account of this if the read and write operations are to be performed correctly.

Flash memory technology is able to provide a very high density form of memory.

Flash Memory Advantages

•         Non-volatile memory
•          Easily portable (e.g. USB memory sticks, camera flash cards, etc)
•          Mechanically robust

Flash Memory Disadvantages

•          Higher cost per bit than hard drives
•          Slower than other forms of memory
•          Limited number of write / erase cycles
•          Data must be erased before new data can be written
•          Data typically erased and written in blocks

Magnetic Memories - Material

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How Bubble Memory Works - Link

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Charge Coupled Devices - CCD

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A Charge Coupled Device (CCD) is a highly sensitive photon detector. The CCD is divided up into a large number of light-sensitive small areas (known as pixels) which can be used to build up an image of a scene. A photon of light which falls within the area defined by one of the pixels will be converted into one (or more) electrons and the number of electrons collected will be directly proportional to the intensity of the scene at each pixel. When the CCD is clocked out, the number of electrons in each pixel is measured and the scene can be reconstructed.

The figure below shows a simplified cross section through a CCD. The pixels are defined by the position of electrodes above the CCD. If a positive voltage is applied to the electrode, then this positive potential will attract all of the negatively charged electrons close to the area under the electrode. In addition, any positively charged holes will be repulsed from the area around the electrode. Consequently a potential well will form in which the electrons produced by the incoming photons will be stored.

As more and more light falls onto the CCD, then the potential well surrounding this electrode will attract more and more electrons until the potential well is full. To prevent this happening the light must be prevented from falling onto the CCD for example, by using a shutter as in a camera. Thus, an image can be made of an object by opening the shutter, "integrating" for a length of time to fill up most of the electrons in the potential well, and then closing the shutter to ensure that the full well capacity is not exceeded. 

An actual CCD will consist of a large number of pixels (i.e., potential wells), arranged horizontally in rows and vertically in columns. The number of rows and columns defines the CCD size, typical sizes are 1024 pixels high by 1024 pixels wide. The resolution of the CCD is defined by the size of the pixels, also by their separation (the pixel pitch). 

CCD Operation

The figure below shows a cross section through a row of a CCD. Each pixel consists of three electrodes IØ1, IØ2, and IØ3. Only one of these electrodes is required to create the potential well, but other electrodes are required to transfer the charge out of the CCD. The upper section of the figure (section 1) shows charge being collected under one of the electrodes. To transfer the charge out of the CCD, a new potential well can be created by holding IØ3 high, the charge is now shared between IØ2 and IØ3 (section 2). If IØ2 is now taken low, the charge will be fully transferred under electrode IØ3 (section 3). To continue clocking out the CCD, taking IØ1 high and then taking IØ3 low will ensure that the charge cloud now drifts across under the IØ1 electrodes. As this process is continued, the charge cloud will progress either down the column, or across the row, depending upon the orientation of the electrodes.

The figure below (clocking diagram) shows the progression under which each electrode is held high and low to ensure that charge is transferred through the CCD.

Initially, IØ2 is high - usually to around 12V, and the charge is held under that electrode as in (1) previously. When IØ3 is held high, and IØ2 is taken low (usually 0 V), the charge migrates under the IØ3 electrode (as in (2)). Finally, taking IØ1 high and IØ3 low transfers the charge under IØ1 (as in (3)). This process is repeated in transfer 2 and transfer 3, the charge has now been moved three pixels along. This process is known as charge coupling (hence CCD).

For most of the CCD, the electrodes in each pixel are arranged so that the charge is transferred downwards along the columns. Hence, during the CCD clocking operation, rows are transferred downwards to the final row (the readout register) which is used to transfer the charge in each pixel out of the CCD so it can be measured.

In the read out register, the electrodes are arranged so that the charge is transferred in the horizontal direction, along the readout register. 

The final process on the CCD is the reading of each pixel so that the size of the associated charge cloud can be measured. At the end of the readout register is an amplifier which measures the value of each charge cloud and converts it into a voltage.

MOS Dynamic RAM Cell

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Memory cells of a dynamic RAM memory consist of capacitor storing electric charges hence logic voltage levels. A bit cell constitutes a transistor with a capacitor interconnected to the line that selects a memory row and to the bit line in the word (bit read and write lines). The figure below shows such a bit cell based on a MOS FET.

 A write takes place as a result of row line selection (positive voltage) and insertion through a bit line of the voltage that corresponds to the stored bit: 0 V for logical zero and the positive voltage for one. For logical one, the capacitor will charge through the conducting transistor to the positive voltage. For zero, the transistor will be turned off and the condenser will discharge if loaded or it will remain not charged (in both cases the condenser plate at the transistor side will reach 0V potential).

On read, a row line will be set to the positive potential and the transistor will be turned on. If the condenser was charged (the bit cell was storing one), the positive voltage from the condenser plate will be transferred into the bit line (readout of one) after which the capacitor discharges through the bit line. If the capacitor was not charged, 0 V will be transferred to the bit line i.e. a logical zero, stored in this cell. After readout of a bit cell, the condenser has to be charged again to restore the previous contents of the memory cell. It is done by execution of the read cycle for the same information. A data-readout from dynamic RAM memory is destructive and in this memory a read cycle is always followed by a write cycle.

A semiconductor dynamic RAM memory is a volatile memory, since charged capacitors are subject to spontaneous discharging. The reason for this is the leakage that results from impurities in the crystalline structure of silicon. Therefore, dynamic RAM memory requires periodic refreshing of stored data. This is done by special refresh circuits, which are always added as an extension of the proper data storing circuitry.

University Model Examination - Digital Electronics - 4BPH6C2

              Part - A               

1.Convert the decimal number 65.6 into hexadecimal.
2.State distributive laws of Boolean algebra.
3.Simplify the Boolean expression A(A+B+AB).
4.What is the difference between Karnaugh map and truth table.
5.What is meant by flip-flop?
6.How many flip-flops are required to construct a MOD-9 counter.
7.Write the equivalent analog voltage of (11011001)₂  if the full scale voltage is 5 V.
8.Write note on resolution of an ADC.
9.What is the advantage of a PROM over ROM?
10.What is a magnetic bubble memory?

Part - B

11.(a) Describe the function of an AND gate with its truth table.

(OR)

     (b)State and prove De Morgan's Theorem 

12.(a) Explain the working of Half Adder.

(OR)

     (b) Construct and simplify K-map for the expression f(A,B,C,D) = ∑(0,1,4,6,7,8,9,10,11,15).

13.(a) Describe the action of an RS flip-flop with neat circuit diagram and truth table.

(OR)

     (b) Explain the working of Johnson counter.

14.(a) How does a simultaneous ADC operates?

(OR)

     (b) Explain the counter type ADC.

15.(a) Explain the function of a MOS Static RAM cell.

(OR)

     (b) Discuss the construction details of  magnetic disc memories.

Part - C

16. Explain how NOR gate can be used a universal building block.

17. Explain the working of an 8421 BCD Binary adder.

18. With a neat diagram, explain the action of a 4-bit shift register. 

19. Describe the working of a weighted registor type D/A converter.

20.What is a PROM? Explain how a PROM can be programmed with neat diagrams.

MOS Static RAM Cell

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Static random access memory (SRAM) can retain its stored information as long as power is supplied. This is in contrast to dynamic RAM (DRAM) where periodic refreshes are necessary. The term ``random access'' means that in an array of SRAM cells each cell can be read or written in any order, no matter which cell was last accessed.

The structure of a 6 MOS FET SRAM cell, storing one bit of information, is shown in the following figure.

The core of the cell is formed by two CMOS inverters, where the output potential of each inverter (V_out) is fed as input into the other (V_in). This feedback loop stabilizes the inverters to their respective state.

The access transistors and the word and bit lines, WL and BL, are used to read and write from or to the cell. In standby mode the word line is low, turning the access transistors off. In this state the inverters are in complementary state. When the p-channel MOSFET of the left inverter is turned on, the potential  V_l,out is high and the p-channel MOSFET of inverter two is turned off, V_r,out is low.

To write information the data is imposed on the bit line and the inverse data on the inverse bit   line,.

Then the access transistors are turned on by setting the word line to high. 

As the driver of the bit lines is much stronger it can assert the inverter transistors. As soon as the information is stored in the inverters, the access transistors can be turned off and the information in the inverter is preserved.

For reading the word line is turned on to activate the access transistors while the information is sensed at the bit lines.

Programming Bipolar PROM

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Programming Bipolar PROM

ROM stands for Programmable Read Only Memory. Unlike ordinary ROMs, which are programmed at the manufacturer’s site, PROMs are programmed by the users.So, user can load a program into the PROM according to their own specifications. This is an advantage of PROM over ROM. They are also known as Write Once Memory (WOM). PROM is made by connecting the address lines to the data lines by a decoder with connections between decoder o/p lines and data lines made by bipolar transistors with fuses at their emitters. To program the PROM appropriate fuse links are flown by sending a high current pulse through the fuses. This process is illustrated below using 2 address lines and 4 data line with a decoder connecting them.

Initially the PROM from the manufacturer contains bipolar transistor fuse links between decoder lines are all intact as shown in the following schematic diagram.

In such a case, the output of all the data lines is logic 1 irrespective of the address on the address line. At the user site user can selectively flow the fuses by sending a high current pulse through them leaving logic 0s at selected data lines for specific addresses.  For an example, for the following diagram shown with flown fuses the data read for all the possible addresses are given in the table below.

ADDRESS		DATA
A0	A1	D3	D2	D1	D0
0	0	0	1	0	0
0	1	0	1	0	1
1	0	1	0	0	1
1	1	0	0	1	0

The programming is done through a programmer called PROM burner. Three technologies exist for making fusible links at the emitters of bipolar transistors. They are nichrome metal links, poly silicon links and pn junction links.

Digital Model University Questions

Resolution and Accuracy of an ADC

Resolution of an ADC:

Resolution of an ADC is defined as the smallest voltage increment corresponding to a 1 bit LSB change.It is the smallest analog voltage an ADC can resolve.

Accuracy of an ADC:

Accuracy of an ADC determines how close the actual digital output is to the theoretically expected digital output for a given analog input. The accuracy of an ADC is a function of its internal circuitry and noise from the external sources connected to the ADC.

Successive Approximation ADC

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Successive Approximation type ADC is the most widely used and popular ADC method. The conversion time is maintained constant in successive approximation type ADC, and is proportional to the number of bits in the digital output, unlike the counter and continuous type A/D converters. The basic principle of this type of A/D converter is that the unknown analog input voltage is approximated against an n-bit digital value by trying one bit at a time, beginning with the MSB. The principle of successive approximation process for a 4-bit conversion is explained here. This type of ADC operates by successively dividing the voltage range by half, as explained in the following steps.

(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital equivalent voltage is compared with the unknown analog input voltage.

(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second MSB is set to 1. Comparison is made as given in step (1) to decide whether to retain or reset the second MSB.

The above steps are more accurately illustrated with the help of an example. Let us assume that the 4-bit ADC is used and the analog input voltage is V_A = 11 V. when the conversion starts, the MSB bit is set to 1.

Now V_A = 11 V  >  V_D = 8V = [1000]₂

Since the unknown analog input voltage V_A is higher than the equivalent digital voltage V_D, as discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows
V_D = 12 V = [1100]₂

Now V_A = 11 V  <  V_D = 12 V = [1100]₂

Here now, the unknown analog input voltage V_A is lower than the equivalent digital voltage V_D. As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as V_D = 10 V = [1010]₂

Now again V_A = 11 V  > V_D = 10 V = [1010]₂

Again as discussed in step (2) V_A>V_D, hence the third MSB is retained to 1 and the last bit is set to 1. The new code word is V_D = 11 V = [1011]₂

Now finally V_A = V_D , and the conversion stops.

It consists of a successive approximation register (SAR), DAC and comparator. The output of SAR is given to n-bit DAC. The equivalent analog output voltage of DAC, V_D is applied to the non-inverting input of the comparator. The second input to the comparator is the unknown analog input voltage V_A. The output of the comparator is used to activate the successive approximation logic of SAR.

When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made logic 0, so that the trial code becomes 1000.

Advantages:
1.  Conversion time is very small.
2.  Conversion time is constant and independent of the amplitude of the analog input signal V_A.

Disadvantages:
1. Circuit is complex.
2. The conversion time is more compared to flash type ADC.