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Memory cells of a dynamic RAM memory consist of capacitor
storing electric charges hence logic voltage levels. A bit cell
constitutes a transistor with a capacitor interconnected to the line that
selects a memory row and to the bit line in the word (bit read and write
lines). The figure below shows such a bit cell based on a MOS FET.
A write takes place as
a result of row line selection (positive voltage) and insertion through a bit
line of the voltage that corresponds to the stored bit: 0 V for logical zero
and the positive voltage for one. For logical one, the capacitor will charge
through the conducting transistor to the positive voltage. For zero, the
transistor will be turned off and the condenser will discharge if loaded or it
will remain not charged (in both cases the condenser plate at the transistor
side will reach 0V potential).
On read, a row line will be set to the positive potential and
the transistor will be turned on. If the condenser was charged (the bit cell
was storing one), the positive voltage from the condenser plate will be
transferred into the bit line (readout of one) after which the capacitor
discharges through the bit line. If the capacitor was not charged, 0 V will be
transferred to the bit line i.e. a logical zero, stored in this cell. After
readout of a bit cell, the condenser has to be charged again to restore the
previous contents of the memory cell. It is done by execution of the read cycle
for the same information. A data-readout from dynamic RAM memory is destructive
and in this memory a read cycle is always followed by a write cycle.
A semiconductor dynamic RAM memory is a volatile memory,
since charged capacitors are subject to spontaneous discharging. The reason for
this is the leakage that results from impurities in the crystalline structure
of silicon. Therefore, dynamic RAM memory requires periodic refreshing of
stored data. This is done by special refresh circuits, which are always added
as an extension of the proper data storing circuitry.