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In
a MOS dynamic RAM cell data is stored as charge on a capacitor. As charge is continuously
leaked from the capacitor, the data stored (bit 1) will be lost if not being
refreshed from an external circuit. Such a circuit which constantly restores
the charge on a capacitor representing bit 1 is called a refresh circuit. A
basic refresh circuit shown in the following diagram is described below.
To enable refresh operation R/W
line, ROW line and REFRESH line are made HIGH. This turns ON transistor and
connects capacitor to COLUMN line. As R/W is HIGH, output buffer is
enabled and the stored data bit is applied to the input of refresh buffer. The
enabled refresh buffer then produces a voltage on COLUMN line corresponding to
the stored bit and thus replenishing the capacitor with charge.
This process is repeated at a particular frequency to ensure
that the 1 data bit stored in the cell is not lost due to leakage.