ADC – Counter Method

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An n-bit simultaneous ADC requires 2n comparators and this is a huge disadvantage when high resolution is needed. This can be resolved by using a counter type ADC, where a single comparator with variable reference voltage suffices for any desired accuracy.  This type of comparator is shown in the following schematic diagram.




This circuit works as follows. Initially, the counter is reset to all 0s. When a convert signal appears on the start line, the input gate is enabled and the clock pulses are applied to the clock input of the counter. The counter advances through its normal binary count sequence. The counter output feeds a D/A converter and the staircase waveform generated at the output of the D/A converter forms one of the inputs of the comparator. The other input to the comparator is the analogue input signal. Whenever the D/A converter’s output exceeds the analog input voltage, the comparator changes state. The gate is disabled and the counter stops. The counter output at that instant of time is then the required digital output corresponding to the analog input signal.

The counter type A/D converter provides a very good method for digitizing to a high resolution. This method is much simpler than the simultaneous method for higher-resolution A/D converters. The drawback with this converter is that the required conversion time is longer. Since the counter always begins from the all 0s position and counts through its normal binary sequence, it may require as many as 2n counts before conversion is complete. Average conversion time of a counter method ADC is 2n-1  clock cycles’ time.

For an example, If there is a four-bit converter and a 1 MHz clock, the average conversion time would be 2n-1 =8 micro seconds. It would be as large as 0.5 ms for a 10-bit converter of this type at a 1 MHz clock rate. In fact, the conversion time doubles for each bit added to the converter. Thus, the resolution can be improved only at the cost of a longer conversion time. This makes the counter-type A/D converter unsuitable for digitizing rapidly changing analog signals.

8421 BCD Adder

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A BCD adder is a digital circuit to add two BCD numbers and produces the sum as a BCD number. When a BCD number is added to another BCD number using a 4-bit binary full adder, following 3 cases may arise:

     1.       Sum is less than or equal to 9 with carry 0.
     2.       Sum is greater than 9 with carry 0.
     3.       Sum is less than or equal to 9 with carry 1.

In the first case the sum is a valid BCD number and no further process is needed, but in the second and third cases the sum is not valid and should be converted into BCD numbers. To make such a correction a factor of 6 (in binary) is added to the sum to obtain the final result.

The logic expression to check if the sum of two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 => S3S2S1S0 exceeds 9 is given by,

Y = S3S2 + S3S1

With these points, a BCD adder circuit can be designed as shown in the following diagram.




As shown in the figure, the two BCD numbers, together with input carry, are first added in the top 4-bit binary adder to produce a binary sum. When the output carry is equal to zero (i.e. when sum ≤ 9 and Cout = 0) nothing (zero) is added to the binary sum. When it is equal to one (i.e. when sum > 9 or Cout = 1), binary 0110 is added to the binary sum through the bottom 4-bit binary adder. The output carry generated from the bottom binary adder is ignored as it is already available at the output carry terminal.

II Internal Test - Atomic and Nuclear Physics - 7BPH4C1

Part A - 5 x 2 = 10

  1. What is normal Zeeman effect?
  2. Distinguish between anomalous and normal Zeeman effect.
  3. Write down the Larmor's theorem.
  4. State Mosley's law.
  5. Write note on characteristic x-rays.

Part B - 2 x 5 = 10


  1. Derive the expression for Bohr magneton Explain its significance.
  2. Derive Bragg's law of x-ray diffraction.
Part C - 2 x 10 = 20

  1. Discuss the quantum theory of normal Zeeman effect.
  2. Give the theory of Compton effect. Discuss its' experimental verification.